Elenco Electronics MO-1251 Manual de usuario descargar pdf (Pagina 61)

CLK

INPUT

01

ENABLE

CI

-K

02 03

114

45188

OR

'. 45208

RESET

01

ENABLE

CLK

02 03

45188

OR

45208

RESET

04

Ol

ENABLE

CLK

02 03 04

' : 4518B

OR

45208

RESET

FIG. 16-THE

4518B

OR

4520B

counters cascaded

for ripple operation.

7

10

1

9

2

3

4

6

16

EP

CLOCK

ENABLE

ET

INPUTS

CLEAR

LOAD

CLOCK

Pl

P2

P3

P4

401606

TO

401638

01

14

02

13

12

04 11

CARRY

15

OUT

18

FIG. 17- PINOUT DIAGRAM OF

THE

40160B TO 40163B

range

of

programma-

ble 4 -bit counters.

negative

-edge triggering,

the

feed

the

clock to the ENABLE pin

and tie the

CLOCK pin

low.

Each counter can be

asynchronously cleared

by a high

level on

the RESET pin. The outputs of

both dual IC's must

be decoded exter-

nally to drive

a

7- segment

display.

Notice

that those counters don't

have

a CARRY OUTPUT. In order to

cas-

cade stages,

triggering on the nega-

tive -edge of the clock is required.

As

UP

/DOWN

o

PRESET ENABLE

o

1

1 1 1

10

J1

J2 J3

J4

U

D

PE

1

C-I

IC1

4029B

CO

01

Q2

Q3

Q4 B D

CLK

16

I 1 I

I

CLK

o

BINARY

/DECADE

O

9

15

8

1 I I I

1011 V

J1

J2

J3

J4

U D PE

161

C-I

Ql

02

I

IC2

40298

CO

03

NM/

CLK

7

II

9

15

8

1111

JI

J2

CI

10

1

V

J3

J4

U D

PE

16

C-0

8

01 02 Q3

04 B/D

CLK

IC3

4029B

15

FIG. 20-

HERE'S HOW TO CASCADE 4029B's for

synchronous parallel-

clocking.

the RBI of

the next LSB

counter, and

so

on,

to the first

counter

in

the

fractions

chain.

CLK

INPUT

11111E1111

+v

NOTES:

10

16

15 2

3

CLEAR

EP

LOAD

CARRY

CLK

OUT

P1

P2

P3

P4

401608 IS

DECADE COUNTER WITH ASYNCHRONOUS CLEAR.

40161B IS

BINARY

COUNTER WITH ASYNCHRONOUS

CLEAR

40162B IS DECADE COUNTER WITH ASYNCHRONOUS

CLEAR

4

8

5

6

40163B

IS BINARY

COUNTER WITH ASYNCHRONOUS

CLEAR.

FIG. 18-THE

40160B TO 40163B

connected

for normal

counter operation.

1

5

9

10

15

1 4

112 113 1

3 116

V

J1

J2

J3

J4

JAM

INPUTS

PRESET ENABLE

CARRY IN

4029B

BINARY

/DECADE

UP

/DOWN

CLOCK

01

02

03

04

CARRY

OUT

18

6

11

14

2

7

FIG. 19- PINOUT

DIAGRAM

OF THE

40298 presettable

up /down counter.

Least

Significant

Bit' (LSB)

must be

tied low,

and

its RBO

must be

taken to

Keep in mind that

neither

the

4026B nor

the

4033B have

data

latches.

That basically means that the

displays tend to blur

while

the IC's are

going through

a counting cycle. It is,

however, no

tremendous

problem.

Dual

up- counters

The 4518B

and 4520B

are IC's that

house

two counters in

a

single

16 -pin

package.

The 4518B

is a dual decade

counter

with

BCD outputs;

the 4520B

is a dual hexadecimal

(divide-

by -16)

counter

with

a

4 -bit

binary output.

Figure 15 shows

the identical pinout

diagram of the 4518B

and 4520B.

Those

counters can be

clocked

using

either positive- or

negative -

edge

triggering.

For positive

-edge

triggering, feed

the clock

to the CLOCK

pin and

tie the ENABLE pin

high. For

shown

in

figure 16,

the Q4

OUTPUT of

each counter

is fed

to the ENABLE

INPUT

of the

following

stage, which

must

also have

its

CLOCK pin tied low.

Counters

that

preset

As shown

in Fig. 17,

the 40160B

to

40163B

series

of presettable

up -coun-

ters have identical

pinouts.

By preset-

table

we mean that

the DECODED

OUTPUTS

Q1-Q4 can

be preset to start

counting from

any number

that is fed

into the four

PRESET PI -P4 input

pins

-

sometimes

called JAM inputs. The

pre-

setting function

is not limited only

to

start -up, but

can also be used during

the counting sequence;

the decoded

outputs can thus be cleared

back to the

original preset inputs

at any time.

The 40160B

and 40162B are

de-

cade

dividers,

while

the 40161B

and

40163B

are binary

dividers. Also, the

clear function for

the 40162B

and

40163B

is synchronous with

the

clock. That

means a low

on the CLEAR

sets all outputs

low on the rising

edge

of the next

clock pulse.

On

the other

hand,

the clear function

for the

40160B

and 40161B

is asynchronous.

A low

level on

that CLEAR sets all

outputs

low regardless

of the clocks

state.

Figure

18 shows how to

connect

any of the 40160

to 40163 IC's

as a

normal

counter. All

counters in that

series

have two clock-

enable pins, EP

and ET,

which

must

be tied high for

normal

counting

operation. Those

67

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